1. Field of the Invention
The present invention relates to a semiconductor package having such a structure that a package substrate and a semiconductor chip are coupled to each other.
2. Description of Related Art
A COX (Chip On X) structure in which a bare semiconductor chip is directly mounted on a wiring board has been generally known as a semiconductor package structure using a bare technique. The COX structure is mainly classified into a structure based on a flip chip bonding technique and a structure based on a wire bonding technique.
FIGS. 1A and 1B show a conventional semiconductor package structure based on the flip chip bonding technique. More specifically, FIG. 1A is a cross-sectional view of the semiconductor package structure, and FIG. 1B is a plan view of the semiconductor package structure.
In the semiconductor package shown in FIGS. 1A and 1B, a semiconductor chip 51 is put face down on a package substrate 50 serving as a base. A bump 52 serving as a chip electrode is formed on the surface (the lower surface in the figures) of the semiconductor chip 51, and the semiconductor chip 51 and the package substrate 50 are electrically and mechanically connected to each other through the bump 52. Further, a wiring pattern 53 is formed on the chip-mounted surface (the upper surface in the figures) of the package substrate 50, and an embedded through hole is formed at the pattern end portion of the wiring pattern 53.
According to the package structure as described above, even when the size of the semiconductor chip 51 is varied, the same-size package substrate 50 may be used commonly to these semiconductor chips having different sizes by forming the wiring pattern 53 in accordance with the chip size of each semiconductor chip.
FIG. 2 is a cross-sectional view showing the conventional structure of a semiconductor package based on the wire bonding technique.
In the semiconductor package shown in FIG. 2, a semiconductor chip 61 is put face up on a package substrate 60 serving as a base. A chip electrode (not shown) is formed on the surface of the semiconductor chip 61, and the chip electrode is electrically connected to an embedded through hole electrode 63 of the package substrate 60 through a wire 62 such as a metal wire or the like.
In the package structure, even when the size of the semiconductor chip 61 is varied, the same-size package substrate 60 may be used commonly to these semiconductor chips having different sizes by performing wire bonding in accordance with the chip size.
However, the conventional semiconductor package has the following problems.
First, in the case of the semiconductor package shown in FIG. 1, the electrode position (bump position) is varied in accordance with the size of the semiconductor chip 51. Therefore, when semiconductor chips 51 having the same number of electrodes are mounted, for example when a semiconductor chip 51 which is smaller in size than described above as shown in FIG. 3A is mounted, a package substrate 50 having a wiring pattern 53 which is matched with the semiconductor chip 51 must be prepared. Accordingly, even when semiconductor chips 51 have the same number of electrodes, a package substrate 50 which is exclusive to each size of semiconductor chip must be prepared, and it greatly obstructs standardization of parts.
Further, in the case of the semiconductor package shown in FIG. 2, the bonding length which is required to keep proper wire bonding quality, that is, a fixed permissible range is given to the horizontal distance BL between the bonding position at the chip side and the bonding position at the substrate side. Therefore, if the horizontal distance exceeds the permissible range, for example when the bonding length BL is excessively short as compared with the chip size shown in FIG. 3B, the wire 63 comes into contact with the chip edge to induce a short-circuit failure. Conversely, when it is excessively long, there occurs such a disadvantage that the wire 62 is hung down. Accordingly, a limitation is imposed on the chip size of semiconductor chips which can be mounted on the same-size package substrate 60. Further, when inner coat agent 64 having a large contraction rate is provided as show in FIG. 3C, the wire 62 is greatly deformed due to the contraction of the inner coat agent in the progress of the hardening of the inner coat agent, so that a limitation is also imposed on selection of materials.
In addition, each of the semiconductor packages shown in FIGS. 1A and 1B and FIG. 2 has such a structure that the semiconductor chip 51 (61) is mounted on the package substrate 50 (60), and thus the thickness of each part is added, so that the total thickness of the overall package is large. Accordingly, these semiconductor packages cannot support a compact and low-profile design for semiconductor packages which will be required in the future.